The present invention relates to a communication control apparatus for the ATM adaptation layer (AAL layer) in ATM (Asynchronous Transfer Mode) communications and, more particularly, to a communication control apparatus for performing a CRC (Cyclic Redundancy Check) calculation used in AAL type 5 (to be referred to as AAL5 hereinafter).
In ATM communications, the size of communication data is defined by a 53-byte long format called an ATM cell. As shown in FIG. 7, the ATM cell consists of a 5-byte ATM header including a VPI (virtual path identifier) and a VCI (virtual channel identifier), and a 48-byte payload (communication data). The advantage of this system is that since the unit of data transfer has a fixed length, switching in a cell switch that constitutes a communication network can be implemented in hardware and, hence, a very high communication speed is viable.
The protocol layers used in ATM communications have a hierarchical structure, as shown in FIG. 8. Note that an ATM layer is a layer for transferring the above-mentioned 53-byte long cell, and an AAL layer is a layer for segmentation and reassembly of variable-length communication data (called a frame) to be processed in higher layers.
Some types of AAL layers have been defined and, especially, AAL5 is important for a communication means between computers.
FIG. 9 shows the structural format of a frame (CPCS-PDU) used in AAL5.
Referring to FIG. 9, 4 bytes at the end of the frame are a check code for detecting errors, and a CRC (Cyclic Redundancy Check) code is used.
In error detection, the absence of errors can be determined when mod-2 divisions using a generation polynomial (G(x)) are made from the first data of the frame, and the CRC result yields a specific value (V(x)). ##EQU1##
Since the frame with the above-mentioned structure is divided into ATM cells to be transferred discretely, it is difficult to simultaneously perform a CRC calculation for the entire communication data. In view of this problem, in the conventional method, each time an incoming cell is received, a CRC calculation is performed and the intermediate result is held. When the subsequent arriving cell is received, a CRC calculation is restarted from the intermediate value obtained so far.
The basic principle of error detection based on the CRC calculation will be explained below.
The CRC calculation uses mod-2 cyclic codes.
An information polynomial I(x) of degree n is given by: EQU I(x)=I.sub.0 +I.sub.1 x.sup.1 +I.sub.2 x.sup.2 +. . . +I.sub.n-1 x.sup.n-1( 2)
A generation polynomial G(x) of degree m is given by: EQU G(x)=G.sup.0 +G.sub.1 x.sup.1 +G.sub.2 x.sup.2 +. . . +G.sub.m-1 x.sup.m-1( 3)
The information polynomial I(x) is multiplied with x.sup.m, and the product is divided by G(x). Let Q(x) be the quotient, and R(x) be the remainder. Then, we have: EQU I(x)x.sup.m =Q(x)G(x)+R(x) (4)
Communication data A(x) is sent as: EQU A(x)=R(x)+I(x)x.sup.m ( 5)
In this case, since equation (6) below holds, A(x) can be divided by G(x) at the receiving side: ##EQU2## When some error has been generated in the communication data A(x), the data A(x) cannot be divided by G(x). Hence, the receiving side can detect the presence/absence of errors by determining whether or not A(x) can be divided by G(x).
In a CRC arithmetic circuit used in AAL5, it is defined that the initial value of an F/F (flip-flop) that constitutes the circuit is set to be all "1"s, and hence, CRC checking is attained by checking whether or not the calculation result is concordant with V(x) above.
The cell reassembly processing will be briefly explained below.
In reassembly processing of ATM cells upon reception of these cells, a management table shown in FIG. 10 is used to support a plurality of communication lines and to manage the intermediate state during reassembly of a frame.
The management table shown in FIG. 10 stores a reassembly status variable that indicates a state before start, a state during reassembly, disposal processing, and the like, and also stores frame length data that indicates the data length of already received data associated with ATM cells received so far, the start and end addresses of received data, the intermediate value of the CRC calculation, and the like.
FIG. 11 is a block diagram showing the arrangement of a conventional AAL communication control apparatus, and FIG. 12 is a timing chart showing the operation timings of the apparatus shown in FIG. 11.
Referring to FIG. 11, the communication control apparatus comprises a cell reception unit 101 for receiving cells, a frame reassembly unit 102 for reassembling a frame using cells received by the cell reception unit 101, a data holding circuit 103 for holding data of cells received by the cell reception unit 101, a CRC circuit 104 for calculating the CRC value of the currently received cell on the basis of data held in the data holding circuit 103 and the CRC intermediate value of cells received so far, a checking circuit 105 for checking the received data for any errors on the basis of the CRC value calculated by the CRC circuit 104, and a memory interface 107 for interfacing with a management data memory 106 which stores the above-mentioned management data.
In this arrangement, when an ATM cell is received by the cell reception unit 101, a VPI and VCI stored in the ATM header are supplied to the memory interface 107 to specify a management table of the corresponding VC (Virtual Channel), and the specified management data are read out from the management data memory 106 that holds VC management data.
The frame reassembly unit 102 checks the reassembly status variable, and if the reassembly status variable indicates a state before start, frame management control data is initialized, and a value indicating the state during reassembly is set in the reassembly status variable. Received data is stored in the internal data memory (not shown) of the communication control apparatus, and its start and end addresses are written back to the management data memory 106 via the memory interface 107.
Since the first cell of the frame has been received, the CRC circuit 104 is set with a prescribed value (data of all bits="1"), and performs a CRC calculation for data of the currently received cell.
Note that a considerable amount of time is required until the VPI and VCI are supplied to the memory interface 107 and the reassembly status variable is confirmed, and a CRC calculation cannot be started before then. For this reason, the received data is temporarily stored in the data holding circuit 103. Upon completion of reception of the cell, the intermediate value of the CRC calculation is written back to the management data memory 106 via the memory interface 107.
When this VC receives the subsequent incoming ATM cell, since the reassembly status variable indicates the state during reassembly, the payload of this ATM cell is added to the end of the frame indicated by the end address, and the end address and the frame length are updated. The CRC calculation is performed for the currently received data using the value read out from the management data memory 106 as an initial value, and the calculation result is written back to the management data memory 106 upon completion of reception.
If the received ATM cell is normal and indicates the end of the frame, the calculation result is checked by the checking circuit 105 when the CRC calculation up to data at the end of the cell is completed, and if the calculation result is in agreement with V(x) above, the absence of errors is determined, thus ending the reassembly processing of the frame. Then, the entire frame is transferred to a higher layer.
Note that information indicating the end of the frame used in the AAL layer is stored in a portion of the ATM header, but a detailed description of its detailed structure will be omitted for the sake of simplicity.
As the state-of-the-art technique associated with the CRC calculation, the following inventions are known. That is, in the invention of a CRC code confirmation method and apparatus described in Japanese Patent Laid-Open No. 7-15354, a partial CRC code is generated using a predetermined initial setting value in units of subblocks received by a transmission apparatus that transmits a data block while dividing it into subblocks, a CRC code for the entire data block is reassembled using partial CRC codes, and the reassembled CRC code is confirmed. In the invention of a cell synchronization circuit described in Japanese Patent Laid-Open No. 3-98346, XOR (exclusive OR) circuit networks that perform partial CRC calculations are cascade-connected via latch circuits to realize a CRC calculation in a pipeline manner. In the invention of a CRC arithmetic method described in Japanese Patent Laid-Open No. 3-85923, ROM tables that store CRC calculation results in units of divided data sequences are arranged in correspondence with data sequences obtained by dividing an input data sequence, and the outputs from the ROM tables are XORed to calculate a CRC calculation result for the input data sequence. Furthermore, in the invention described in Japanese Patent Laid-Open No. 6-53942, CRC codes in units of cells are calculated and are sent via special-purpose control wires to check CRC codes in units of cells.
As described above, the AAL layer must perform retrieval of the management table address using the VPI and VCI, and reading and updating of the table contents every time an ATM cell is received. In particular, the CRC calculation cannot be started for the currently received cell data until the CRC intermediate value is read out from the management table in the management data memory and is set in the CRC circuit, resulting in the following drawbacks.
(1) A large number of data holding circuits 103 (registers) for temporarily holding received data are required. For example, when data is input as an 8-bit parallel signal, and loading of management data is delayed by five clocks, data for 40 bits must be stored.
(2) Since the timing of the CRC calculation is delayed, the CRC calculation cannot be completed at the same timing as the end of reception of cells. Normally, the calculation continues after reception of the subsequent cell is started.
(3) Since the end timing of the CRC calculation is delayed, the write operation to the management data memory is delayed accordingly, and the determination timing of the end of frame reassembly is also delayed.
(4) When ATM cells that belong to an identical VC are successively received, management data for the subsequent cell must be immediately loaded. Meanwhile, since the write operation of management data for the previous cell is delayed, the updating and look-up operations of management data replace each other, thus disturbing proper accesses.